1. Field of the Invention
The present invention relates to a control LSI (large scaled integrated circuit), and more specifically to a numerical data processor for transferring output data of a multiplier to an adder for Fourier transform.
2. Description of Related Art
Conventional numerical data processors have been such that, for fast Fourier transform (called "FFT" hereinafter), output data of a multiplier is transferred to an adder by means of a transfer instruction in software. In the FFT, furthermore, when an address of data in a butterfly operation is rearranged, a translated address has been generated by performing a bit inversion from a most significant bit (MSB) to a least significant bit (LSB) in a software manner.
In the above mentioned conventional numerical data processors, when the FFT is carried out, since the address translation of the data has been performed in the software manner, the base number is 2 in ordinary cases.
The following is a basic algorithm of the butterfly operation in the FFT having the base number of 2: EQU D0=D0+W0.times.D1 EQU D1=D0-W0.times.D1
where W0 is a rotational factor when 360.degree. is halved.
In the FFT having the base number of 2, therefore, the number of butterfly operations can be expressed as follows because of restriction in algorithm: EQU (number of data)/2.times.log.sub.2 (number of data)
Accordingly, the arithmetic operation needs a considerable time. In this connection, even if a base number larger than 2 is used, since the address rearrangement of the data has been performed in the software manner, necessary processing becomes too complicated, and therefore, the operation speed cannot be improved.